StorAIge

The main objective of the storAIge project is the development and industrialization of FDSOI 28nm and next generation embedded Phase Change Memory (ePCM) world-class semiconductor technologies, allowing the prototyping of high performance, Ultra low power and secured & safety System on Chip (SoC) solutions enabling competitive Artificial Intelligence (AI) for Edge applications. The main challenge addressed by the project is on one hand to handle the complexity of sub-28nm ‘more than moore’ technologies and to bring them up at a high maturity level and on the other hand to handle the design of complex SoCs for more intelligent, secure, flexible, low power consumption and cost effective. The project is targeting chipset and solutions with very efficient memories and high computing power targeting 10 Tops per Watt.
The development of the most advanced automotive microcontrollers in FDSOI 28nm ePCM will be the support technology to demonstrate the high performances path as well as the robustness of the ePCM solution. The next generation of FDSOI ePCM will be main path for general purpose advanced microcontrollers usable for large volume Edge AI application in industrial and consumer markets with the best compromise on three requirements: performances, low power and adequate security.
On top of the development and industrialization of silicon process lines and SoC design, StorAIge will also address new design methodologies and tools to facilitate the exploitation of these advanced technology nodes, particularly for high performance microcontrollers having AI capabilities. Activities will be performed to setup robust and adequate Security and Safety level in the final applications, defining and implementing the good ‘mixture’ and tradeoff between HW and SW solutions to speed up adoption for large volume applications.

ARCES participates to the project as third part of IU.NET consortium.